Renesas Electronics /R7FA6M1AD /GPT_ODC /GTDLYCR2

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Interpret as GTDLYCR2

DLYEN0=0, DLYEN2=0, DLYEN3=0, DLYEN1=0, DLYBS3=0, DLYBS0=0, DLYBS2=0, DLYBS1=0

Description

PWM Output Delay Control Register2

Fields

DLYBS0	PWM Delay Generation Circuit bypass for channel 0 0 (0): Bypass delay generation circuit of channel 0 1 (1): Do not bypass delay generation circuit of channel 0.
DLYBS1	PWM Delay Generation Circuit bypass for channel 1 0 (0): Bypass delay generation circuit of channel 1 1 (1): Do not bypass delay generation circuit of channel 1.
DLYBS2	PWM Delay Generation Circuit bypass for channel 2 0 (0): Bypass delay generation circuit of channel 2 1 (1): Do not bypass delay generation circuit of channel 2.
DLYBS3	PWM Delay Generation Circuit bypass for channel 3 0 (0): Bypass delay generation circuit of channel 3 1 (1): Do not bypass delay generation circuit of channel 3.
DLYEN0	PWM Delay Generation Circuit enable for channel 0 0 (0): Enable delay generation circuit of channel 0 1 (1): Disable delay generation circuit of channel 0.
DLYEN1	PWM Delay Generation Circuit enable for channel 1 0 (0): Enable delay generation circuit of channel 1 1 (1): Disable delay generation circuit of channel 1.
DLYEN2	PWM Delay Generation Circuit enable for channel 2 0 (0): Enable delay generation circuit of channel 2 1 (1): Disable delay generation circuit of channel 2.
DLYEN3	PWM Delay Generation Circuit enable for channel 3 0 (0): Enable delay generation circuit of channel 3 1 (1): Disable delay generation circuit of channel 3

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